eSi-3264

• 32/64-bit RISC architecture
• 16 or 32 general purpose registers
• 104 basic instructions and 10 addressing modes
• Dual and quad SIMD multiply with 64-bit accumulate
• Complex multiply with rounding
• Optional single/double IEEE 754 floating point unit (FPU)
• Supports up to 90 user-defined instructions
• 5-stage pipeline
• Optional memory management unit (MMU)
• Configurable instruction and data caches (1-64kB, direct mapped or 2 or 4 way associative)
• AMBA AXI or AHB interconnect and APB peripheral bus
• User and supervisor modes
• Up to 32 vectored interrupts plus NMI and system call
• HW nested and prioritizable interrupts
• Fast interrupt response time of 6-9 cycles
• JTAG or serial debug, with optional trace
• Up to 4.12 CoreMark per MHz
• Multiprocessor support
• Intermixed 16 and 32-bit instructions result in exceptional code density without compromising performance
• High quality IP:
  • Verilog RTL
  • DFT ready
  • Silicon proven
• C and C++ software development using license-free toolchain, under industry standard Eclipse IDE
• Easy migration path to cacheless or non-SIMD version

The eSi-3264 32/64-bit CPU is the top-of-the-range member in the eSi-RISC family of processor cores from eSi-RISC. It is targeted specifically for applications needing DSP functionality with minimal silicon area and very low power. The processor features a fully-pipelined dual/quad-MAC unit with 32 or 64-bit accumulator, making the eSi-3264 ideal for audio, high-accuracy sensor hub, motion control and touch screen applications.

Support for 8, 16 and 32-bit SIMD (Single Instruction Multiple Data) operations with integrated multiplication and addition performed in a single cycle also targets filtering and complex arithmetic operations.

The processor features optional instruction and data caches that can be configured in size (from 1- 64kB) and associativity (direct mapped, 2 or 4-way associative) to increase performance when accessing off-chip memory. The optional paged memory management unit (MMU) enables the implementation of virtual memory or memory protection. The 5-stage pipeline allows extremely high clock frequencies to be achieved.

The eSi-3264′s instruction set includes everything you would expect in a high performance processor. There are also a number of optional application specific instructions and addressing modes. For example, a set of IEEE-754 compliant single and double precision floating point instructions are available. Bit manipulation instructions such as bitfield extract and insert, count leading zeros, population count, find first set and bit reverse can be included. Integer square root, absolute value, min/max, CRC and parity are also available. 64-bit SIMD instructions with 8, 16, or 32-bit elements exploit data parallelism and reduce loop counts. Wait-for-interrupt instructions allow fast entry to low power states, enabling clock and power gating.

For those applications that require extreme performance or ultra low power operation, user-defined instructions and registers can be implemented.

Instructions are encoded in either 16 or 32-bits, with all of the commonly used instructions being encoded in 16-bits, maximizing code density and improving cache performance.

The processor supports both user and supervisor operating modes, with privileged instructions and memory areas, to allow an O/S kernel to be fully protected from user applications.

Hardware debug facilities include hardware breakpoints, watchpoints, trace, performance counters, null pointer detection and single-stepping for fast debugging of ROM, FLASH and RAM based programs.

The toolchain is based upon the industry standard GNU toolchain, which includes an optimising C and C++ compiler, assembler, linker, debugger, simulator and binary utilities. All these tools can be driven by the customisable Eclipse IDE or from the command line.

The debugger can connect to HW targets via a low-cost USB- JTAG adaptor or serial link and RTL simulations via a Verilog PLI library.

Complete C and C++ libraries are supplied. Ports of Micrium’s uC/OS-II RTOS, Express Logic’s ThreadX, FreeRTOS and the lwIP TCP/IP stack are available.

The toolchain is available for both Windows and Linux hosts and is available to use at no additional cost.

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The eSi-3264 is delivered as a Verilog RTL IP core. The design is target technology independent and DFT ready, supporting full scan insertion for all flip flops and memory BIST. Example scripts are provided for popular EDA tools.

A selection of AMBA peripherals can be supplied with the core, including: UART, SPI, I2C™, I2S, Timer, PWM, Watchdog, GPIO, PS/2, RTC, Ethernet MAC, USB, FIFO, Scatter-Gather DMA, AES, SHA, ECC and a quad-SPI Flash interface. By using an industry standard bus, a wide range of 3rd party IP cores are compatible with the eSi-3264.

eSi-RISC can generate a multilayer AHB matrix and APB bus to connect the eSi-3264 CPU, memory and peripherals, according to a customer’s specification.